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EPM570GF100I 数据表(PDF) 36 Page - Altera Corporation |
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EPM570GF100I 数据表(HTML) 36 Page - Altera Corporation |
36 / 86 page 2–28 Chapter 2: MAX II Architecture I/O Structure MAX II Device Handbook © October 2008 Altera Corporation Each I/O bank has dedicated VCCIO pins that determine the voltage standard support in that bank. A single device can support 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a different standard. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. For example, when VCCIO is 3.3 V, Bank 3 can support LVTTL, LVCMOS, and 3.3-V PCI. VCCIO powers both the input and output buffers in MAX II devices. The JTAG pins for MAX II devices are dedicated pins that cannot be used as regular I/O pins. The pins TMS, TDI, TDO, and TCK support all the I/O standards shown in Table 2–4 on page 2–27 except for PCI. These pins reside in Bank 1 for all MAX II devices and their I/O standard support is controlled by the VCCIO setting for Bank 1. PCI Compliance The MAX II EPM1270 and EPM2210 devices are compliant with PCI applications as well as all 3.3-V electrical specifications in the PCI Local Bus Specification Revision 2.2. These devices are also large enough to support PCI intellectual property (IP) cores. Table 2–5 shows the MAX II device speed grades that meet the PCI timing specifications. Figure 2–23. MAX II I/O Banks for EPM1270 and EPM2210 (Note 1), (2) Notes to Figure 2–23: (1) Figure 2–23 is a top view of the silicon die. (2) Figure 2–23 is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations. I/O Bank 2 I/O Bank 3 I/O Bank 4 I/O Bank 1 All I/O Banks Support ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS Also Supports the 3.3-V PCI I/O Standard |
类似零件编号 - EPM570GF100I |
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类似说明 - EPM570GF100I |
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