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EP1C20F400C8ES 数据表(PDF) 11 Page - Altera Corporation

部件名 EP1C20F400C8ES
功能描述  Cyclone FPGA Family
Download  106 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1C20F400C8ES 数据表(HTML) 11 Page - Altera Corporation

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Altera Corporation
2–5
May 2008
Preliminary
Logic Elements
With the LAB-wide
addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks
[5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrackTM interconnect's inherent low
skew allows clock and control signal distribution in addition to data.
Figure 2–4 shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
Logic Elements
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by a LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 2–5.
labclkena1
labclk2
labclk1
labclkena2
asyncload
or labpre
syncload
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclr1
labclr2
synclr
addnsub
6


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