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EP2SGX90F 数据表(PDF) 31 Page - Altera Corporation |
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EP2SGX90F 数据表(HTML) 31 Page - Altera Corporation |
31 / 314 page Altera Corporation 2–23 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture Programmable Run Length Violation The word aligner supports a programmable run length violation counter. Whenever the number of the continuous ‘0’ (or ‘1’) exceeds a user programmable value, the rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles. The maximum run values supported are shown in Table 2–7. Running Disparity Check The running disparity error rx_disperr and running disparity value rx_runningdisp are sent along with aligned data from the 8B/10B decoder to the FPGA. You can ignore or act on the reported running disparity value and running disparity error signals. Bit-Slip Mode The word aligner can operate in either pattern detection mode or in bit-slip mode. The bit-slip mode provides the option to manually shift the word boundary through the FPGA. This feature is useful for: ■ Longer synchronization patterns than the pattern detector can accommodate ■ Scrambled data stream ■ Input stream consisting of over-sampled data This feature can be applied at 10-bit and 16-bit data widths. The word aligner outputs a word boundary as it is received from the analog receiver after reset. You can examine the word and search its boundary in the FPGA. To do so, assert the rx_bitslip signal. The rx_bitslip signal should be toggled and held constant for at least two FPGA clock cycles. For every rising edge of the rx_bitslip signal, the current word boundary is slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit slipping shifts a complete round of bus width, the word boundary is back to the original boundary. Table 2–7. Maximum Run Length (UI) Mode PMA Serialization 8 Bit 10 Bit 16 Bit 20 Bit Single-Width 128 160 — — Double-Width — — 512 640 |
类似零件编号 - EP2SGX90F |
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类似说明 - EP2SGX90F |
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