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EP2SGX60D 数据表(PDF) 23 Page - Altera Corporation |
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EP2SGX60D 数据表(HTML) 23 Page - Altera Corporation |
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23 / 314 page  Altera Corporation 2–15 October 2007 Stratix II GX Device Handbook, Volume 1 Stratix II GX Architecture ■ Lane deskew ■ Rate matcher ■ 8B/10B decoder ■ Byte deserializer ■ Byte ordering ■ Receiver phase compensation FIFO buffer Receiver Input Buffer The Stratix II GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standard at rates up to 6.375 Gbps. The common mode voltage of the receiver input buffer is programmable between 0.85 V and 1.2 V. You must select the 0.85 V common mode voltage for AC- and DC-coupled PCML links and the 1.2 V common mode voltage for DC-coupled LVDS links. The receiver has programmable on-chip 100-, 120-, or 150- Ωdifferential termination for different protocols, as shown in Figure 2–12. The receiver’s internal termination can be disabled if external terminations and biasing are provided. The receiver and transmitter differential termination resistances can be set independently of each other. Figure 2–12. Receiver Input Buffer Programmable Termination The programmable termination can be statically set in the Quartus II software. Figure 2–13 shows the setup for programmable receiver termination. The termination can be disabled if external termination is provided. Programmable Termination Input Pins Differential Input Buffer Programmable Equalizer |
类似零件编号 - EP2SGX60D |
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类似说明 - EP2SGX60D |
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