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EP2SGX60C 数据表(PDF) 94 Page - Altera Corporation

部件名 EP2SGX60C
功能描述  Stratix II GX Device
Download  314 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP2SGX60C 数据表(HTML) 94 Page - Altera Corporation

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Altera Corporation
Stratix II GX Device Handbook, Volume 1
October 2007
Digital Signal Processing (DSP) Block
The DSP block is divided into four block units that interface with four
LAB rows on the left and right. Each block unit can be considered one
complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local
interconnect region is associated with each DSP block. Like a LAB, this
interconnect region can be fed with 16 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. R4 and C4
routing resources can access the DSP block’s local interconnect region.
The outputs also work similarly to LAB outputs. Eighteen outputs from
the DSP block can drive to the left LAB through direct link interconnects
and 18 can drive to the right LAB through direct link interconnects. All 36
outputs can drive to R4 and C4 routing interconnects. Outputs can drive
right- or left-column routing.
Figures 2–59 and 2–60 show the DSP block interfaces to LAB rows.
Figure 2–59. DSP Block Interconnect Interface
A1[17..0]
B1[17..0]
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
A4[17..0]
B4[17..0]
OA[17..0]
OB[17..0]
OC[17..0]
OD[17..0]
OE[17..0]
OF[17..0]
OG[17..0]
OH[17..0]
DSP Block
R4, C4 & Direct
Link Interconnects
R4, C4 & Direct
Link Interconnects


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