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EP4SE110 数据表(PDF) 37 Page - Altera Corporation

部件名 EP4SE110
功能描述  Stratix IV Device
Download  40 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP4SE110 数据表(HTML) 37 Page - Altera Corporation

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Chapter 1: DC and Switching Characteristics
1–35
Glossary
© December 2008
Altera Corporation
Stratix IV Device Handbook, Volume 4
F
f
HS CLK
Left/Right PLL input clock frequency.
f
HS DR
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate
(f
HS DR = 1/TUI), non-DPA.
f
HS DRDPA
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate
(f
HS DRDP A = 1/TUI), DPA.
G
——
H
——
I
——
J
J
HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).
JTAG Timing
Specifications
JTAG Timing Specifications are in the following figure:
K
——
L
——
M
——
N
——
O
——
PPLL
Specifications
The block diagram shown in the following figure highlights the PLL Specification parameters:
Diagram of PLL Specifications (1)
Note:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
Q
——
RR
L
Receiver differential input discrete resistor (external to Stratix IV device).
Table 1–45. Glossary Table
Letter
Subject
Definitions
TDO
TCK
tJPZX
t
JPCO
tJPH
t JPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
Core Clock
External Feedback
Reconfigurable in User Mode
Key
CLK
N
M
PFD
Switchover
VCO
CP
LF
CLKOUT Pins
GCLK
RCLK
fINPFD
fIN
fVCO
fOUT
fOUT_EXT
Counters
C0..C9


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