EP1C20F400C7ES datasheet(33/106 Pages) ALTERA

部件名	EP1C20F400C7ES

功能描述	Cyclone FPGA Family

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制造商	ALTERA [Altera Corporation]

网页	http://www.altera.com

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Altera Corporation

2–27

May 2008

Preliminary

Embedded Memory

Figure 2–19. Input/Output Clock Mode in Simple Dual-Port Mode

Notes (1), (2)

Notes to Figure 2–19:

(1)

All registers shown except the rden register have asynchronous clear ports.

(2)

Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both

read and write operations.

6

D

ENA

Q

D

ENA

Q

D

ENA

Q

D

ENA

Q

D

ENA

Q

data[ ]

D

ENA

Q

wraddress[ ]

address[ ]

Memory Block

256 ´ 16

512 ´ 8

1,024 ´ 4

2,048 ´ 2

4,096 ´ 1

Data In

Read Address

Write Address

Write Enable

Read Enable

Data Out

outclken

inclken

inclock

outclock

wren

rden

6 LAB Row

Clocks

To MultiTrack

Interconnect

D

ENA

Q

byteena[ ]

Byte Enable

Write

Pulse

Generator

类似零件编号 - EP1C20F400C7ES

制造商	部件名	数据表	功能描述
Altera Corporation	EP1C20F400C7ES	1Mb / 94P	Cyclone FPGA Family
	EP1C20F400C7ES	1Mb / 104P	Cyclone FPGA Family Data Sheet
	EP1C20F400C7ES	1Mb / 106P	Section I. Cyclone FPGA Family Data Sheet

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类似说明 - EP1C20F400C7ES

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Altera Corporation	EP1C20F400	1Mb / 94P	Cyclone FPGA Family
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EP1C20F400C7ES 数据表(PDF) 33 Page - Altera Corporation

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类似零件编号 - EP1C20F400C7ES

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EP1C20F400C7ES 数据表(PDF) 33 Page - Altera Corporation

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类似零件编号 - EP1C20F400C7ES

类似说明 - EP1C20F400C7ES

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