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EP1M120 Datasheet(数据表) 4 Page - Altera Corporation

部件型号  EP1M120
说明  Programmable Logic Device Family
下载  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
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EP1M120 Datasheet(HTML) 4 Page - Altera Corporation

 
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Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Mercury devices include other features for performance such as quad-
port RAM, CAM, general purpose PLLs, and dedicated circuitry for
implementing multiplier circuits. Table 4 shows Mercury performance.
Note to Table 4:
(1)
The clock tree supports up to 400 MHz. Although the registered performance for these designs exceed 400 MHz,
they are limited by the clock tree limit.
Configuration
The logic, circuitry, and interconnects in the Mercury architecture are
configured with CMOS SRAM elements. Mercury devices are
reconfigurable and are 100% tested prior to shipment. As a result, test
vectors do not have to be generated for fault coverage purposes. Instead,
the designer can focus on simulation and design verification. In addition,
the designer does not need to manage inventories of different ASIC
designs; Mercury devices can be configured on the board for the specific
functionality required.
Mercury devices are configured at system power-up with data stored in
an Altera® serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices, which configure Mercury devices via a serial data stream.
Mercury devices can be configured in under 70 ms. Moreover, Mercury
devices contain an optimized interface that permits microprocessors to
configure Mercury devices serially or in parallel, synchronously or
asynchronously. This interface also enables microprocessors to treat
Mercury devices as memory and to configure the device by writing to a
virtual memory location, simplifying reconfiguration.
Table 4. Mercury Performance
Application
Resources Used
Performance
LEs
ESBs
-5 Speed
Grade
-6 Speed
Grade
-7 Speed
Grade
Units
16-bit loadable counter (1)
16
0
400
400
400
MHz
32-bit loadable counter (1)
32
0
400
400
400
MHz
32-bit accumulator (1)
32
0
400
400
400
MHz
32-to-1 multiplexer
27
0
1.864
2.466
2.723
ns
32
× 64 asynchronous FIFO
103
2
290
258
242
MHz
8-bit, 37-tap FIR filter
251
1
290
240
205
MSPS




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