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EP1M120 数据表(PDF) 18 Page - Altera Corporation |
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EP1M120 数据表(HTML) 18 Page - Altera Corporation |
18 / 86 page 18 Altera Corporation Mercury Programmable Logic Device Family Data Sheet Figure 7. Mercury LE Notes to Figure 7: (1) FastLUT interconnect uses the data4 input. (2) LAB carry-out can only be generated by LE 4 and/or LE 10. Each LE’s programmable register can be configured for D, T, JK, or SR operation. The register’s clock, clock enable, and clear control signals can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the register is bypassed and the output of the LUT drives directly to the outputs of the LE. Each LE has four data inputs that can drive the internal LUT. One of these inputs has a shorter delay than the others, improving overall LE performance. This input is chosen automatically by the Quartus II software as appropriate. labclk1 labclk2 labclr labpre Carry-In1 Carry-In0 LAB Carry-In Clock & Clock Enable Select LAB Carry-Out (2) Carry-Out1 Carry-Out0 Look-Up Table (LUT) Carry Chain to Local, Row, and Column Routing to Local, Row, and Column Routing Programmable Register PRN CLRN DQ ENA Register Bypass Packed Register Select Chip-Wide Reset labclkena1 labclkena2 Synchronous Load and Clear Logic LAB-wide Synchronous Load LAB-wide Synchronous Clear Asynchronous Clear/Preset/ Load Logic data1 data2 data3 data4 (1) FastLUT Routing to next LE LE Clock Enable |
类似零件编号 - EP1M120 |
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类似说明 - EP1M120 |
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