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EP1M120 数据表(PDF) 66 Page - Altera Corporation

部件名 EP1M120
功能描述  Programmable Logic Device Family
Download  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1M120 数据表(HTML) 66 Page - Altera Corporation

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Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Figure 32 shows the timing requirements for the JTAG signals.
Figure 32. Mercury JTAG Waveforms
Table 19 shows the JTAG timing parameters and values for Mercury
devices.
Table 19. Mercury JTAG Timing Parameters & Values
Symbol
Parameter
Min
Max
Unit
tJCP
TCK
clock period
100
ns
tJCH
TCK
clock high time
50
ns
tJCL
TCK
clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
ns
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock to output
35
ns
tJSZX
Update register high impedance to valid output
35
ns
tJSXZ
Update register valid output to high impedance
35
ns
TDO
TCK
tJPZX
t
JPCO
tJPH
t JPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
tJSSU
tJSH
t
JSCO
tJSXZ


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