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EP1M120 Datasheet(数据表) 6 Page - Altera Corporation

部件型号  EP1M120
说明  Programmable Logic Device Family
下载  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
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EP1M120 Datasheet(HTML) 6 Page - Altera Corporation

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Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
Mercury device I/O pins are evenly distributed across the entire device
area; other Altera device families have I/O pins placed on the device
periphery. Mercury device I/O pin placement allows for higher I/O count
at a given die size; pad size is no longer a limiting issue. Each I/O pin is
fed by an IOE. IOEs are grouped in IOE row bands from the top to the
bottom of the device. IOE row bands are separated by several LAB rows.
LABs from the associated LAB row closest to the I/O row band drive IOEs
through the local interconnect. This feature allows fast clock-to-output
times when a pin is driven by any of the 10 LEs in the adjacent associated
LAB. Each IOE contains a bidirectional buffer along with an input register,
output register, output enable (OE) register, and input latch for DDR.
When used with a global clock, these dedicated registers provide
exceptional bidirectional I/O performance.
IOEs provide a variety of features, such as 3.3-V, 64-bit, 66-MHz PCI
compliance; 3.3-V, 64-bit, 133-MHz PCI-X compliance; Joint Test Action
Group (JTAG) boundary-scan test (BST) support; output drive strength
control; slew-rate control; tri-state buffers; bus-hold circuitry;
programmable pull-up resisters; programmable input and output delays;
and open-drain outputs. Mercury devices offer enhanced I/O support,
including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, HSTL,
LVPECL, 3.3-V PCML, 3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3,
CTT, and 3.3-V AGP I/O standards. CDR (up to 1.25 Gbps) and source-
synchronous (up to 840 Mbps) transfers are supported with HSDI
circuitry for LVDS, LVPECL, and 3.3-V PCML I/O standards.
The ESB can implement a variety of memory functions, including CAM,
quad-port RAM, true dual-port RAM, dual- and single-port RAM, ROM,
and FIFO functions. ESBs are grouped into two rows: one at the top and
one at the bottom of the device. Embedding the memory directly into the
die improves performance and reduces die area compared to distributed-
RAM implementations. Moreover, the abundance of cascadable ESBs, in
conjunction with the ability for one ESB to implement two separate
memory blocks, ensures that the Mercury device can implement multiple
wide memory blocks for high-density designs. The ESB’s high speed
ensures the implemention of small memory blocks without any speed
penalty. The abundance of ESBs ensures that designers can create as many
different-sized memory blocks as the system requires. Figure 1 shows an
overview of the Mercury device.




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