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EP1M120 Datasheet(数据表) 5 Page - Altera Corporation

部件型号  EP1M120
说明  Programmable Logic Device Family
下载  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
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EP1M120 Datasheet(HTML) 5 Page - Altera Corporation

 
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Altera Corporation
5
Mercury Programmable Logic Device Family Data Sheet
13
After a Mercury device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Real-time changes
can be made during system operation, enabling innovative reconfigurable
computing applications.
Software
Mercury devices are supported by the Altera QuartusTM II development
system, a single, integrated package that offers HDL and schematic design
entry, compilation and logic synthesis, full simulation and worst-case
timing analysis, SignalTapTM logic analysis, and device configuration. The
Quartus II software also ships with Altera-specific HDL synthesis tools
from Exemplar Logic and Synopsys, and Altera-specific Register Transfer
Level (RTL) and timing simulation tools from Model Technology. The
Quartus II software supports PCs running Windows 98, Windows NT 4.0,
and Windows 2000; UNIX workstations running Solaris 2.6, 7, or 8, or
HP-UX 10.2 or 11.0; and PCs running Red Hat Linux 7.1.
The Quartus II software provides NativeLinkTM interfaces to other
industry-standard PC- and UNIX-workstation-based EDA tools. For
example, designers can invoke the Quartus II software from within the
Mentor Graphics LeonardoSpectrum software, Synplicity’s Synplify
software, and the Synopsys FPGA Express software. The Quartus II
software also contains built-in optimized synthesis libraries; synthesis
tools can use these libraries to optimize designs for Mercury devices. For
example, the Synopsys Design Compiler library, supplied with the
Quartus II development system, includes DesignWare functions
optimized for the Mercury architecture.
For more information on the Quartus II development system, see the
Quartus II Programmable Logic Development System & Software Data Sheet.
Functional
Description
The Mercury architecture contains a row-based logic array to implement
general logic and a row-based embedded system array to implement
memory and specialized logic functions. Signal interconnections within
Mercury devices are provided by a series of row and column
interconnects with varying lengths and speeds. The priority FastTrack
Interconnect structure is faster than other interconnects; the Quartus II
Compiler places design-critical paths on these faster lines to improve
design performance.




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