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EPF6024A 数据表(PDF) 36 Page - Altera Corporation |
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EPF6024A 数据表(HTML) 36 Page - Altera Corporation |
36 / 52 page 36 Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Timing Model The continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and therefore have unpredictable performance. Device performance can be estimated by following the signal path from a source, through the interconnect, to the destination. For example, the registered performance between two LEs on the same row can be calculated by adding the following parameters: ■ LE register clock-to-output delay (tCO + tREG_TO_OUT) ■ Routing delay (tROW + tLOCAL) ■ LE LUT delay (tDATA_TO_REG) ■ LE register setup time (tSU) The routing delay depends on the placement of the source and destination LEs. A more complex registered path may involve multiple combinatorial LEs between the source and destination LEs. Timing simulation and delay prediction are available with the Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point-to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure 19 shows the overall timing model, which maps the possible routing paths to and from the various elements of the FLEX 6000 device. |
类似零件编号 - EPF6024A |
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类似说明 - EPF6024A |
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