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EPF10K10 数据表(PDF) 61 Page - Altera Corporation |
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EPF10K10 数据表(HTML) 61 Page - Altera Corporation |
61 / 128 page Altera Corporation 61 FLEX 10K Embedded Programmable Logic Device Family Data Sheet Table 34. EAB Timing Microparameters Note (1) Symbol Parameter Conditions tEABDATA1 Data or address delay to EAB for combinatorial input tEABDATA2 Data or address delay to EAB for registered input tEABWE1 Write enable delay to EAB for combinatorial input tEABWE2 Write enable delay to EAB for registered input tEABCLK EAB register clock delay tEABCO EAB register clock-to-output delay tEABBYPASS Bypass register delay tEABSU EAB register setup time before clock tEABH EAB register hold time after clock tAA Address access delay tWP Write pulse width tWDSU Data setup time before falling edge of write pulse (5) tWDH Data hold time after falling edge of write pulse (5) tWASU Address setup time before rising edge of write pulse (5) tWAH Address hold time after falling edge of write pulse (5) tWO Write enable to data output valid delay tDD Data-in to data-out valid delay tEABOUT Data-out delay tEABCH Clock high time tEABCL Clock low time |
类似零件编号 - EPF10K10 |
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类似说明 - EPF10K10 |
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