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EPF6010A Datasheet(数据表) 4 Page - Altera Corporation |
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EPF6010A Datasheet(HTML) 4 Page - Altera Corporation |
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4 page 
4 Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Table 4 shows FLEX 6000 performance for more complex designs. Note: (1) The applications in this table were created using Altera MegaCore TM functions. FLEX 6000 devices are supported by Altera development systems; a single, integrated package that offers schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use device- specific features such as carry chains which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development systems include DesignWare functions that are optimized for the FLEX 6000 architecture. The Altera development system runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800. f See the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet for more information. Table 4. FLEX 6000 Device Performance for Complex Designs Note (1) Application LEs Used Performance Units -1 Speed Grade -2 Speed Grade -3 Speed Grade 8-bit, 16-tap parallel finite impulse response (FIR) filter 599 94 80 72 MSPS 8-bit, 512-point fast Fourier transform (FFT) function 1,182 75 63 89 53 109 43 µS MHz a16450 universal asynchronous receiver/transmitter (UART) 487 36 30 25 MHz PCI bus target with zero wait states 609 56 49 42 MHz |
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