数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

EP1SGX40G 数据表(PDF) 59 Page - Altera Corporation

部件名 EP1SGX40G
功能描述  StratixGX FPGA Family
Download  262 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1SGX40G 数据表(HTML) 59 Page - Altera Corporation

Back Button EP1SGX40G Datasheet HTML 55Page - Altera Corporation EP1SGX40G Datasheet HTML 56Page - Altera Corporation EP1SGX40G Datasheet HTML 57Page - Altera Corporation EP1SGX40G Datasheet HTML 58Page - Altera Corporation EP1SGX40G Datasheet HTML 59Page - Altera Corporation EP1SGX40G Datasheet HTML 60Page - Altera Corporation EP1SGX40G Datasheet HTML 61Page - Altera Corporation EP1SGX40G Datasheet HTML 62Page - Altera Corporation EP1SGX40G Datasheet HTML 63Page - Altera Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 59 / 262 page
background image
Altera Corporation
59
Preliminary
Source-Synchronous Signaling with DPA
Figure 43. Misaligned Captured Bits
The dynamic phase selector and synchronizer align the clock and data
based on the power-up of both communicating devices, and the channel
to channel skew. However, the dynamic phase selector and synchronizer
cannot determine the byte boundary, and the data may need to be
byte-aligned. The dynamic phase aligner’s data realignment circuitry
shifts data bits to correct bit misalignments.
The Stratix GX circuitry contains a data-realignment feature controlled by
the logic array. Stratix GX devices perform data realignment on the
parallel data after the deserialization block. The data realignment can be
performed per channel for more flexibility. The data alignment operation
requires a state machine to recognize a specific pattern. The procedure
requires the bits to be slipped on the data stream to correctly align the
incoming data to the start of the byte boundary.
The DPA uses its realignment circuitry and the global clock for data
realignment. Either a device pin or the logic array asserts the internal
rx_channel_data_align
node to activate the DPA data-realignment
circuitry. Switching this node from low to high activates the realignment
circuitry and the data being transferred to the logic array is shifted by
one bit. The data realignment block cannot be bypassed. However, if the
rx_channel_data_align
is not turned on (through the altvlds
MegaWizard Plug-In Manager), or when it is not toggled, it will only act
as a register latency.
A state machine and additional logic can monitor the incoming parallel
data and compare it against a known pattern. If the incoming data pattern
does not match the known pattern, designers can activate the
rx_channel_data_align
node again. Repeat this process until the
realigner detects the desired match between the known data pattern and
incoming parallel data pattern.
0
1
2
3
4
5
6
7
3
4
5
6
7
0
1
2
Correct Alignment
Incorrect Alignment


类似零件编号 - EP1SGX40G

制造商部件名数据表功能描述
logo
Altera Corporation
EP1SGX40 ALTERA-EP1SGX40 Datasheet
456Kb / 34P
   1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
EP1SGX40 ALTERA-EP1SGX40 Datasheet
2Mb / 182P
   Package Information Datasheet for Mature Altera Devices
EP1SGX40 ALTERA-EP1SGX40 Datasheet
633Kb / 36P
   Enhanced Configuration (EPC) Devices Datasheet
EP1SGX40 ALTERA-EP1SGX40 Datasheet
621Kb / 36P
   This datasheet describes enhanced configuration (EPC) devices
EP1SGX40 ALTERA-EP1SGX40 Datasheet
633Kb / 36P
   Enhanced Configuration (EPC) Devices Datasheet
More results

类似说明 - EP1SGX40G

制造商部件名数据表功能描述
logo
Altera Corporation
EP1C20F400 ALTERA-EP1C20F400 Datasheet
1Mb / 94P
   Cyclone FPGA Family
EP1C20F ALTERA-EP1C20F Datasheet
1Mb / 106P
   Cyclone FPGA Family
logo
Xilinx, Inc
XC3S50 XILINX-XC3S50_08 Datasheet
5Mb / 216P
   Spartan-3 FPGA Family
XC3S50 XILINX-XC3S50_05 Datasheet
1Mb / 198P
   Spartan-3 FPGA Family
XC3S50A-4TQG144C XILINX-XC3S50A-4TQG144C Datasheet
5Mb / 132P
   Spartan-3A FPGA Family
XC3S200A-4FTG256I XILINX-XC3S200A-4FTG256I Datasheet
5Mb / 132P
   Spartan-3A FPGA Family
DS001 XILINX-DS001 Datasheet
1,015Kb / 99P
   Spartan-II FPGA Family
logo
Altera Corporation
EP4CE115F29I7N ALTERA-EP4CE115F29I7N Datasheet
372Kb / 14P
   Cyclone IV FPGA Device Family
EP1C3 ALTERA-EP1C3 Datasheet
1Mb / 104P
   Cyclone FPGA Family Data Sheet
EP4CE6E22I7N ALTERA-EP4CE6E22I7N Datasheet
498Kb / 14P
   Cyclone IV FPGA Device Family Overview
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com