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EP1SGX40D 数据表(PDF) 69 Page - Altera Corporation

部件名 EP1SGX40D
功能描述  StratixGX FPGA Family
Download  262 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1SGX40D 数据表(HTML) 69 Page - Altera Corporation

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Altera Corporation
69
Preliminary
Logic Elements
Figure 50. LE in Dynamic Arithmetic Mode
Note to Figure 50:
(1)
The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in arithmetic mode. The carry-select chain uses the redundant carry
calculation to increase the speed of carry functions. The LE is configured
to calculate outputs for a possible carry-in of 1 and carry-in of 0 in
parallel. The carry-in0 and carry-in1 signals from a lower-order bit
feed forward into the higher-order bit via the parallel carry chain and feed
into both the LUT and the next portion of the carry chain. Carry-select
chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel
pre-computation of carry chains. Because the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delay between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Stratix GX
architecture to implement high-speed counters, adders, multipliers,
parity functions, and comparators of arbitrary width.
Figure 51 shows the carry-select circuitry in an LAB for a 10-bit full adder.
One portion of the LUT generates the sum of two bits using the input
signals and the appropriate carry-in bit; the sum is routed to the output
of the LE. The register can be bypassed for simple adders or used for
data1
LUT
data2
data3
addnsub
(LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
ALD/PRE
CLRN
D
Q
ENA
ADATA
Register chain
connection
LUT
LUT
LUT
Carry-Out1
Carry-Out0
LAB Carry-In
Carry-In0
Carry-In1
(1)
sclear
(LAB Wide)
sload
(LAB Wide)
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
aload
(LAB Wide)
Register Feedback


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