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EP1SGX40D 数据表(PDF) 50 Page - Altera Corporation |
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EP1SGX40D 数据表(HTML) 50 Page - Altera Corporation |
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50 / 262 page  50 Altera Corporation Preliminary Stratix GX FPGA Family Figure 36. Stratix GX High-Speed Interface Serialized in ×10 Mode Figure 37. Transmitter Timing Diagram DPA Block Overview Each Stratix GX receiver channel features a DPA block. The block contains a dynamic phase selector for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. Designers can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel by using a separate deserializer shown in Figure 38. PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Stratix GX Logic Array Transmitter Circuit Parallel Register Serial Register Fast PLL TXOUT+ TXOUT − ×W TXLOADEN TXLOADEN Internal ×1 clock Internal ×10 clock Receiver data input n – 1 n – 0 9 8 7 6 5 4 3 2 1 0 |
类似零件编号 - EP1SGX40D |
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类似说明 - EP1SGX40D |
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