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EPXA4 数据表(PDF) 4 Page - Altera Corporation |
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EPXA4 数据表(HTML) 4 Page - Altera Corporation |
4 / 16 page 4 Altera Corporation Excalibur Device Overview General Description Devices belonging to the Excalibur family combine an unparalleled degree of integration and programmability. They offer an outstanding embedded system development platform, providing a cost-efficient access to leading-edge embedded processors and PLD performance. The Excalibur family offers a variety of PLD densities and memory sizes to fit a wide range of applications and requirements. The high- performance embedded architecture is ideal for compute-intensive as well as high data-bandwidth applications. Figure 1 shows the structure of the Excalibur devices. The embedded stripe contains the processor core, peripherals, and memory subsystem. The amounts of single- and dual-port memory vary as listed in Table 1 on page 3. Figure 2 on page 5 shows the system architecture of the embedded stripe and the interfaces to the PLD portion of the devices. This architecture promotes maximum integration with minimal system cost and allows the embedded stripe and PLD to be independently optimized for maximum performance. Figure 1. Excalibur Architecture PLL Timer UART Interrupt Controller Watchdog Timer 128 Kbytes SRAM 64 Kbytes DPRAM 32 Kbytes SRAM 16 Kbytes DPRAM 256 Kbytes SRAM 128 Kbytes DPRAM Embedded Processor Stripe PLD DPRAM XA1 XA4 XA10 Trace Module ARM922T SRAM SRAM SRAM DPRAM DPRAM External Memory Interfaces |
类似说明 - EPXA4 |
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