EP2A15 Datasheet(数据表) 4 Page

4 page

Altera Corporation

APEX II Programmable Logic Device Family Data Sheet

–

LogicLockTM incremental design for intellectual property (IP)

integration and team-based design

–

NativeLinkTM integration with popular synthesis, simulation,

and timing analysis tools

–SignalTap® embedded logic analyzer simplifies in-system design

evaluation by giving access to internal nodes during device

operation

–

Support for popular revision-control software packages,

including PVCS, RCS, and SCCS

Tables 2 and 3 show the APEX II ball-grid array (BGA) and

FineLine BGATM device package sizes, options, and I/O pin counts.

Notes to Table 3:

(1)

All APEX II devices support vertical migration within the same package (e.g., the designer can migrate between the

EP2A15, EP2A25, and EP2A40 devices in the 672-pin FineLine BGA package). Vertical migration means that

designers can migrate to devices whose dedicated pins, configuration pins, LVDS pins, and power pins are the same

for a given package across device densities. Migration of I/O pins across densities requires the designer to cross

reference the available I/O pins using the device pin-outs. This must be done for all planned densities for a given

package type to identify which I/O pins are migratable.

(2)

I/O pin counts include dedicated clock and fast I/O pins.

Table 2. APEX II Package Sizes

Feature

672-Pin

FineLine BGA

724-Pin BGA

1,020-Pin

FineLine BGA

1,508-Pin

FineLine BGA

Pitch (mm)

1.00

1.27

1.00

Area (mm2)

729

1,225

1,089

1,600

Length

× Width (mm × mm)

× 27

× 35

× 33

× 40

Table 3. APEX II Package Options & I/O Pin Count

Notes (1), (2)

Feature

672-Pin

FineLine BGA

724-Pin BGA

1,020-Pin

FineLine BGA

1,508-Pin

FineLine BGA

EP2A15

492

EP2A25

492

536

EP2A40

492

536

735

EP2A70

536

1,060

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