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EP2A15 Datasheet(数据表) 2 Page - Altera Corporation |
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EP2A15 Datasheet(HTML) 2 Page - Altera Corporation |
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2 page 
2 Altera Corporation APEX II Programmable Logic Device Family Data Sheet Notes to Table 1: (1) Each device has 36 input channels and 36 output channels. (2) EP2A15 and EP2A25 devices have 56 input and 56 output channels; EP2A40 and EP2A70 devices have 88 input and 88 output channels. (3) PLL: phase-locked loop. True-LVDS PLLs are dedicated to implement True-LVDS functionality. (4) Two internal outputs per PLL are available. Additionally, the device has one external output per PLL pair (two external outputs per device). ...and More Features ■ I/O features – Up to 380 Gbps of I/O capability – 1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport support on 36 input and 36 output channels that feature clock synchronization circuitry and independent clock multiplication and serialization/deserialization factors – Common networking and communications bus I/O standards such as RapidIO, CSIX, Utopia IV, and POS-PHY Level 4 enabled – 400-megabits per second (Mbps) Flexible-LVDS and HyperTransport support on up to 88 input and 88 output channels (input channels also support LVPECL) – Support for high-speed external memories, including ZBT, QDR, and DDR SRAM, and SDR and DDR SDRAM – Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits – Compliant with 133-MHz PCI-X specifications – Support for other advanced I/O standards, including AGP, CTT, SSTL-3 and SSTL-2 Class I and II, GTL+, and HSTL Class I and II – Six dedicated registers in each I/O element (IOE): two input registers, two output registers, and two output-enable registers – Programmable bus hold feature – Programmable pull-up resistor on I/O pins available during user mode Table 1. APEX II Device Features Feature EP2A15 EP2A25 EP2A40 EP2A70 Maximum gates 1,900,000 2,750,000 3,000,000 5,250,000 Typical gates 600,000 900,000 1,500,000 3,000,000 LEs 16,640 24,320 38,400 67,200 RAM ESBs 104 152 160 280 Maximum RAM bits 425,984 622,592 655,360 1,146,880 True-LVDS channels 36 (1) 36 (1) 36 (1) 36 (1) Flexible-LVDSTM channels (2) 56 56 88 88 True-LVDS PLLs (3) 4444 General-purpose PLL outputs (4) 8888 Maximum user I/O pins 492 612 735 1,060 |
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