SMJ4C1024

1048576 BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS023E – DECEMBER 1988 – REVISED MARCH 1996

7

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST

’4C1024-80

’4C1024-10

’4C1024-12

’4C1024-15

UNIT

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

VOH

High-level

output voltage

IOH = – 5 mA

2.4

2.4

2.4

2.4

V

VOL

Low-level

output voltage

IOL = 4.2 mA

0.4

0.4

0.4

0.4

V

II

Input current

(leakage)

VCC = 5.5 V,

VI = 0 V to 6.5 V,

All other pins = 0 V to VCC

± 10

± 10

± 10

± 10

µA

IO

Output

current

(leakage)

VCC = 5.5 V,

VO = 0 V to VCC,

CAS high

± 10

± 10

± 10

± 10

µA

ICC1

Read- or

write-cycle

current

VCC = 5.5 V,

Minimum cycle

75

70

60

55

mA

ICC2

Standby

current

After one memory cycle,

RAS and CAS high,

VIH = 2.4 V

3

3

3

3

mA

ICC3

Average

refresh

current

(RAS only or

CBR)

VCC = 5.5 V,

Minimum cycle,

RAS cycling,

CAS high (RAS only),

RAS low after CAS low (CBR)

70

65

55

50

mA

ICC4

Average page

current

VCC = 5.5 V,

tPC = minimum,

RAS low,

CAS cycling

50

45

35

30

mA

capacitance over recommended ranges of supply voltage and operating free-air temperature,

f = 1 MHz (see Note 3)

PARAMETER

HL / JD / FQ

HJ

HK

SV

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Ci(A)

Input capacitance, address inputs

6

7

8

9

pF

Ci(D)

Input capacitance, data input

5

5

6

7

pF

Ci(RC)

Input capacitance, strobe inputs

7

7

8

8

pF

Ci(W)

Input capacitance, write-enable input

7

7

7

7

pF

Co

Output capacitance

7

9

10

8

pF

NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25

°C with a 1-MHz signal

applied to the pin under test. All other pins are open.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (see Figure 1)

PARAMETER

ALT.

’4C1024-80

’4C1024-10

’4C1024-12

’4C1024-15

UNIT

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(C)

Access time from CAS low

tCAC

20

25

30

40

ns

ta(CA)

Access time from column address

tAA

40

45

55

70

ns

ta(R)

Access time from RAS low

tRAC

80

100

120

150

ns

ta(CP)

Access time from column precharge

tCPA

40

40

60

75

ns

tdis(CH)

Output disable time after CAS high

(see Note 4)

tOFF

20

25

30

35

ns

NOTE 4: tdis(CH) is specified when the output is no longer driven. The output is disabled by bringing CAS high.