数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

SMJ4C1024-15HK 数据表(PDF) 5 Page - Texas Instruments

部件名 SMJ4C1024-15HK
功能描述  1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
Download  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SMJ4C1024-15HK 数据表(HTML) 5 Page - Texas Instruments

  SMJ4C1024-15HK Datasheet HTML 1Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 2Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 3Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 4Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 5Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 6Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 7Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 8Page - Texas Instruments SMJ4C1024-15HK Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 27 page
background image
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
address (A0 – A9) (continued)
of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row
decoder. CAS is used as a chip select to activate the output buffer as well as to latch the address bits into the
column-address buffer.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable pin can be driven from standard TTL circuits without a pullup
resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write),
data out remains in the high-impedance state for the entire cycle, permitting common input / output operation.
data in (D)
Data-in is written during a write or a read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip latch. In an early-write cycle, W is brought low prior to CAS,
and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or a
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold times
referenced to this signal.
data out (Q)
The 3-state output buffers provide direct TTL compatibility (no pullup resistor required) with a fanout of two
series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle, the output becomes valid after the access time ta(C). The access time
from CAS low (ta(C)) begins with the negative transition of CAS as long as ta(R) and ta(CA) are satisfied. The output
becomes valid after the access time has elapsed and remains valid while CAS is low; when CAS goes high, the
output returns to a high-impedance state. In a delayed-write or read-modify-write cycle, the output follows the
sequence for the read cycle.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 512 rows (A0 – A8). A normal read or write cycle refreshes all bits in each selected row. A RAS-only
operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffer remains
in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden
refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS
at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is used by bringing CAS low earlier than RAS (see parameter td(CLRL)R) and holding it low after
RAS falls (parameter td(RLCH)R). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored and the refresh address is generated internally. The external address is also
ignored during the hidden refresh cycles.
power up
To achieve proper device operation, an initial pause of 200
µs followed by a minimum of eight initialization cycles
is required after full VCC level is achieved.
test function (TF) pin
During normal device operation, TF must be disconnected or biased at a voltage
≤ VCC.


类似零件编号 - SMJ4C1024-15HK

制造商部件名数据表功能描述
logo
Texas Instruments
SMJ416160 TI-SMJ416160 Datasheet
364Kb / 24P
[Old version datasheet]   1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMJ416400 TI-SMJ416400 Datasheet
345Kb / 22P
[Old version datasheet]   4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ418160 TI-SMJ418160 Datasheet
364Kb / 24P
[Old version datasheet]   1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMJ4256 TI-SMJ4256 Datasheet
947Kb / 19P
[Old version datasheet]   262,144-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4256FV TI-SMJ4256FV Datasheet
947Kb / 19P
[Old version datasheet]   262,144-BIT DYNAMIC RANDOM-ACCESS MEMORY
More results

类似说明 - SMJ4C1024-15HK

制造商部件名数据表功能描述
logo
Texas Instruments
TMS418160A TI-TMS418160A Datasheet
355Kb / 24P
[Old version datasheet]   1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY
TMS44409 TI-TMS44409 Datasheet
413Kb / 26P
[Old version datasheet]   1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
TMS626812 TI-TMS626812 Datasheet
565Kb / 40P
[Old version datasheet]   1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMJ416160 TI-SMJ416160 Datasheet
364Kb / 24P
[Old version datasheet]   1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES
TMS44400_1998 TI1-TMS44400_1998 Datasheet
456Kb / 25P
[Old version datasheet]   1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
TMS44400 TI-TMS44400 Datasheet
657Kb / 25P
[Old version datasheet]   1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
logo
Hitachi Semiconductor
HM5118165A HITACHI-HM5118165A Datasheet
1Mb / 27P
   1048576-word x 16-bit Dynamic Random Access Memory
HM5118165B HITACHI-HM5118165B Datasheet
1Mb / 31P
   1048576-word x 16-bit Dynamic Random Access Memory
HM5118160B HITACHI-HM5118160B Datasheet
1Mb / 27P
   1048576-word x 16-bit Dynamic Random Access Memory
logo
Texas Instruments
SMJ44C256 TI-SMJ44C256 Datasheet
330Kb / 21P
[Old version datasheet]   262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com