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74FCT16240ATPVCG4 数据表(PDF) 1 Page - Texas Instruments

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部件名 74FCT16240ATPVCG4
功能描述  16-Bit Buffers/Line Drivers
Download  11 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

74FCT16240ATPVCG4 数据表(HTML) 1 Page - Texas Instruments

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16-Bit Buffers/Line Drivers
CY74FCT16240T
CY74FCT162240T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
SCCS027B - August 1994 - Revised September 2001
Copyright
© 2001, Texas Instruments Incorporated
1CY74FCT162240T
Features
•Ioff supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of –40˚C to +85˚C
• VCC = 5V ± 10%
CY74FCT16240T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce)
<1.0V at VCC = 5V, TA = 25˚C
CY74FCT162240T Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical VOLP (ground bounce)
<0.6V at VCC = 5V, TA= 25˚C
Functional Description
These 16-bit buffer/line drivers are used in memory driver,
clock driver, or other bus interface applications, where high
speed and low power are required. With flow-through pinout
and small shrink packaging, board layout is simplified. The
three-state controls are designed to allow 4-, 8-, or 16-bit
operation.
This
device
is
fully
specified
for
partial-power-down
applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The
CY74FCT16240T
is
ideally
suited
for
driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162240T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for mini-
mal
undershoot
and
reduced
ground
bounce.
The
CY74FCT162240T is ideal for driving transmission lines.
GND
Logic Block Diagrams
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
1OE
34
SSOP/TSSOP
Top View
FCT16240–1
1Y1
1Y2
1Y3
1Y4
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
1A1
1A2
1A3
1A4
1OE
FCT16240–2
2Y1
2Y2
2Y3
2Y4
2A1
2A2
2A3
2A4
2OE
1Y1
1Y2
1Y3
1Y4
1A1
1A2
1A3
1A4
2OE
GND
GND
VCC
2Y3
2Y4
2Y1
2Y2
2A1
2A2
2A3
2A4
VCC
GND
GND
3Y3
3Y4
3Y1
3Y2
3A1
3A2
3A3
3A4
GND
GND
VCC
4Y3
4Y4
4Y1
4Y2
4A1
4A2
4A3
4A4
VCC
GND
3OE
4OE
FCT16240–3
3Y1
3Y2
3Y3
3Y4
3A1
3A2
3A3
3A4
3OE
FCT16240–4
4Y1
4Y2
4Y3
4Y4
4A1
4A2
4A3
4A4
4OE
FCT16240–5


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