1

Data sheet acquired from Harris Semiconductor

SCHS192

Features

• Buffered Inputs

• Three-State Outputs

• Applications in Multiple-Data-Bus Architecture

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Pinout

CD74HC640, CD74HCT640

(PDIP, SOIC)

TOP VIEW

Description

The Harris CD74HC640 and CD74HCT640 silicon-gate

CMOS three-state bidirectional inverting and non-inverting

buffers

are

intended

for

two-way

asynchronous

communication between data buses. They have high drive

current outputs which enable high-speed operation when

driving large bus capacitances. These circuits possess the

low power dissipation of CMOS circuits, and have speeds

comparable to low power Sckottky TTL circuits. They can

drive 15 LSTTL loads. The CD74HC640 and CD74HCT640

are inverting buffers.

Functional Diagram

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

DIR

A0

A1

A2

A3

A4

A6

A5

A7

GND

B0

B1

B2

OE

B3

B4

B5

B6

B7

OUTPUT ENABLE AND

DIRECTION-SELECT LOGIC

A0

A7

OE

DIR

B0

B7

A1

THRU

A6

B1

THRU

B6

GND = 10

January 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1677.1

CD74HC640,

CD74HCT640

High Speed CMOS Logic

Octal Three-State Bus Transceiver, Inverting

[ /Title

(CD74

HC640

,

CD74

HCT64

0)

/Sub-

ject

(High

Speed

CMOS