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CD74HC534 Datasheet(数据表) 6 Page - Texas Instruments

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部件型号  CD74HC534
说明  High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered
下载  9 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 

CD74HC534 Datasheet(HTML) 6 Page - Texas Instruments

   
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6
Output Disable to Q (564)
tPLZ,tPHZ
CL = 50pF
2
-
-
135
-
170
-
205
ns
4.5
-
-
27
-
34
-
41
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
23
-
29
-
35
ns
Output Enable to Q
tPZL,tPZH
CL = 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
38
ns
Maximum Clock Frequency
fMAX
CL = 15pF
5
-
60
-
-
-
-
-
MHz
Output Transition Time
tTHL, tTLH
CL = 50pF
2
-
-
60
-
75
-
90
ns
4.5
-
-
12
-
15
-
18
ns
6
-
-
10
-
13
-
15
ns
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
-32-
-
-
-
-
pF
HCT TYPES
Propagation Delay
tPHL, tPLH
Clock to Output
CL = 50pF
4.5
-
-
35
-
44
-
53
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
Output Disable to Q
tPLZ,tPHZ
CL = 50pF
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
Output Enable to Q
tPZL,tPZH
CL = 50pF
4.5
-
-
35
-
44
-
53
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
Maximum Clock Frequency
fMAX
CL = 15pF
5
-
50
-
-
-
-
-
MHz
Output Transition Time
tTLH, tTHL
CL = 50pF
4.5
-
-
12
-
15
-
18
ns
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
-36-
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD =CPD VCC
2 f
i + ∑ CL VCC
2 f
O where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oC TO
85oC
-55oC TO
125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD74HC534, CD74HCT534, CD74HC564, CD74HCT564




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