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LTC3831EGN-1 数据表(PDF) 7 Page - Linear Technology

部件名 LTC3831EGN-1
功能描述  High Power Synchronous Switching Regulator Controller for DDR Memory Termination
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC3831EGN-1 数据表(HTML) 7 Page - Linear Technology

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LTC3831-1
38311f
PI FU CTIO S
BLOCK DIAGRA
transient response.
FREQSET (Pin 11): Frequency Set. Use this pin to adjust
the free-running frequency of the internal oscillator. With
the pin floating, the oscillator runs at about 300kHz. A
resistor from FREQSET to ground speeds up the oscillator;
a resistor to VCC slows it down.
IMAX (Pin 12): Current Limit Threshold Set. IMAX sets the
threshold for the internal current limit comparator. If IFB
drops below IMAX with TG on, the LTC3831-1 goes into
current limit. IMAX has an internal 12µA pull-down to GND.
Connect this pin to the main VIN supply at the drain of Q1,
through an external resistor to set the current limit thresh-
old. Connect a 0.1
µF decoupling capacitor across this
resistor to filter switching noise.
IFB (Pin 13): Current Limit Sense. Connect this pin to the
switching node at the source of Q1 and the drain of Q2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging IFB.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
VCC (Pin 14): Power Supply Input. All low power internal
circuits draw their supply from this pin. This pin requires
a 4.7
µF bypass capacitor to GND.
PVCC2 (Pin 15): Power Supply Input for BG. Connect this
pin to the main high power supply.
BG (Pin 16): Bottom Driver Output . Connect this pin to the
gate of the lower N-channel MOSFET, Q2. This output
swings from PGND to PVCC2. It remains low when TG is
high or during shutdown mode. To prevent output under-
shoot during a soft-start cycle, BG is held low until TG first
goes high (FFBG in the Block Diagram).
2.2V
QC
1.2V
+
+
R
S
PVCC1
TG
PVCC2
BG
PGND
R+
R
FB
24k
24k
2.66k
2.66k
VREF + 10%
38311 BD
Q
Q
PWM
QSS
VREF
VREF + 10%
MAX
ERR
12
µA
INTERNAL
OSCILLATOR
100
µs DELAY
SHDN
FREQSET
COMP
SS
POWER DOWN
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
+
CC
12
µA
DISABLE
ILIM
IMAX
IFB
VREF
GND
VCC
R
S
ENABLE
BG
Q
POR
FFBG
+
PVCC1
VCC + 2V
V


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