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LTC1860CMS8 数据表(PDF) 12 Page - Linear Technology |
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LTC1860CMS8 数据表(HTML) 12 Page - Linear Technology |
12 / 16 page LTC1860/LTC1861 12 18601fa APPLICATIONS INFORMATION LTC1861 OPERATION Operating Sequence The LTC1861 conversion cycle begins with the rising edge of CONV. After a period equal to tCONV, the conversion is finished. If CONV is left high after this time, the LTC1861 goes into sleep mode. The LTC1861’s 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being trans- mitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND (or AGND). A zero code will occur when the “+” input minus the “–” input equals zero. Full scale occurs when the “+” input minus the “–” input equals VREF minus 1LSB. See Figure 5. Both the “+” and “–” inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the “–” input in differential mode is grounded, a rail-to-rail input span will result on the “+” input. Figure 4. LTC1861 Operating Sequence Figure 5. LTC1861 Transfer Curve CONV SDI SCK 12 11 10 9 8 7 6 5 4 3 2 1 SDO B11 B10 B8 B6 B4 B2 B0* Hi-Z B9 B7 B5 B3 B1 S/D O/S DON’T CARE DON’T CARE tCONV 1860 F04 SLEEP MODE *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY Hi-Z tSMPL VIN* *VIN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) REFER TO TABLE 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 • • • 1860 F05 MUX ADDRESS Table 1. Multiplexer Channel Selection SGL/DIFF 1 1 0 0 ODD/SIGN 0 1 0 1 CHANNEL # 0 + + – 1 + – + GND – – 186465 TBL1 SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE |
类似零件编号 - LTC1860CMS8 |
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类似说明 - LTC1860CMS8 |
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