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LTC1860IS8-PBF 数据表(PDF) 11 Page - Linear Technology

部件名 LTC1860IS8-PBF
功能描述  Î¼Power, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC1860IS8-PBF 数据表(HTML) 11 Page - Linear Technology

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LTC1860/LTC1861
11
18601fa
APPLICATIONS INFORMATION
LTC1860 OPERATION
Operating Sequence
The LTC1860 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV, the conversion is
finished. If CONV is left high after this time, the LTC1860
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1860 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
Analog Inputs
The LTC1860 has a unipolar differential analog input. The
converter will measure the voltage between the “IN+
and “IN” inputs. A zero code will occur when IN+ minus
INequals zero. Full scale occurs when IN+ minus IN
equals VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN
is grounded and VREF is tied to VCC, a rail-to-rail input
span will result on “IN+” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1860 (and the
LTC1861 MSOP package) defines the full-scale range of
the A/D converter. These ADCs can operate with reference
voltages from VCC to 1V.
Figure 1. LTC1860 Operating Sequence
Figure 3. LTC1860 with Rail-to-Rail Input Span
Figure 2. LTC1860 Transfer Curve
CONV
tCONV
SCK
SDO
12
11
10
9
8
7
6
5
4
3
2
1
B11 B10
B8
B6
B4
B2
B0*
Hi-Z
Hi-Z
B9
B7
B5
B3
B1
SLEEP MODE
tSMPL
tsuCONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER
VIN*
*VIN = IN
+ – IN
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
1860 F02
1
2
3
4
8
7
6
5
VREF
IN+
IN
GND
VCC
SCK
SDO
CONV
LTC1860
1860 F03
VIN = 0V TO VCC
VCC
1 F
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS


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