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LT6105HDCB-TRPBF 数据表(PDF) 15 Page - Linear Technology |
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LT6105HDCB-TRPBF 数据表(HTML) 15 Page - Linear Technology |
15 / 20 page LT6105 15 6105fa Error Sources The current sense system uses an amplifier, current mirrors and external resistors to apply gain and level shifting. The output is then dependent on the matching characteristics of the current mirrors, characteristics of the amplifier such as gain and input offset, as well as matching of external resistors. Ideally, the circuit output is: VV R R VI R OUT SENSE OUT IN SENSE SENSE SENSE == •; • In this case, the only error is due to resistor mismatch, which provides an error in gain only. Mismatch in the internal current mirror adds to gain error but is trimmed to less than 0.3%. Offset voltage and sense input current are the main cause of any additional error. Error Due to Input Offset Voltage Dynamic range is inversely proportional to the input offset voltage. Dynamic range can be thought of as the maximum VSENSE divided by VOS. The offset voltage of the LT6105 is typically only ±100μV. Error Due to Sense Input Offset Current Input offset current or mismatches in input bias current will introduce an additional input offset voltage term. Typical input offset current is 0.05μA. Lower values of RIN will keep this error to a minimum. For example, if RIN = 100Ω, then the additional offset is 5μV. Output Current Limitations Due to Power Dissipation The LT6105 can deliver up to 1mA continuous current to the output pin. This output current, IOUT, is the mirrored current which flows through RIN2 and enters the current sense amp via the +IN pin for V–IN > 1.6V, and exits out of –IN through RIN1 for V–IN < 1.6V. The total power dissipa- tion due to input currents, PIN, and the dissipation due to internal mirrored currents, PQ: PTOTAL = PIN + PQ PIN = (V+IN) • IRIN2; V–IN > 1.6V or PIN = (V+ – (V–IN)) • IRIN1; V–IN < 1.6V Since the current exiting –IN is coming from V+, the voltage is V+ – V–IN. Taking the worst case V–IN = 0V, the above equation becomes: PIN ≅ V+ • IRIN1, for V–IN < 1.6V. The power dissipated due to internal mirrored currents: PQ = 2 • IOUT • V+ The factor of 2 is the result of internal current shifting and 1:1 mirroring. At maximum supply and maximum output current, the total power dissipation can exceed 100mW. This will cause significant heating of the LT6105 die. In order to prevent damage to the LT6105, the maximum expected dissipation in each application should be calculated. This number can be multiplied by the θJA value listed in the Pin Configuration section to find the maximum expected die temperature. This must not be allowed to exceed 150°C, or performance may be degraded. As an example, if an LT6105 in the MSOP package is to be run at VS+ = 44V and V+ = 36V with 1mA output current at 80°C ambient: PQ(MAX) = 2 • IOUT(MAX) • V+ = PQ(MAX) = 72mW PIN(MAX) = IRIN2(MAX) • V+IN(MAX) = 44mW TRISE = θJA • PTOTAL(MAX) TMAX = TAMBIENT + TRISE TMAX must be < 150°C PTOTAL(MAX) = 116mW and the maximum die temperature will be 109°C. If this same circuit must run at 125°C ambi- ent, the maximum die temperature will increase to 150°C. Note that supply current, and therefore PQ, is proportional to temperature. Refer to the Typical Performance Charac- teristics section. In this condition, the maximum output current should be reduced to avoid device damage. The DCB package, on the other hand, has a lower θJA and subsequently, a lower die temperature increase than the MSOP. With the same condition as above, the DCB will rise only 7.5°C to 87.5°C and 132.5°C, respectively. It is important to note that the LT6105 has been designed to provide at least 1mA to the output when required, and can deliver more under large VSENSE conditions. Care must be taken to limit the maximum output current by proper choice of sense resistor and input resistors. APPLICATIONS INFORMATION |
类似零件编号 - LT6105HDCB-TRPBF |
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类似说明 - LT6105HDCB-TRPBF |
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