A1225DX-PQC datasheet(50/84 Pages) ACTEL

部件名	A1225DX-PQC

功能描述	Integrator Series FPGAs: 1200XL and 3200DX Families

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制造商	ACTEL [Actel Corporation]

网页	http://www.actel.com

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50 / 84 page

Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s

50

Discontinued – v3.0

A322 00DX Timing Char act eristics (continued)

(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

3.3V ‘Std’

Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

TTL Output Module Timing1

tDLH

Data-to-Pad High

3.7

4.3

4.9

5.8

8.3

6.8

ns

tDHL

Data-to-Pad Low

4.5

5.3

6.0

7.1

10.1

8.3

ns

tENZH

Enable-Pad Z to High

4.8

5.6

6.4

7.5

10.7

8.8

ns

tENZL

Enable-Pad Z to Low

5.2

6.0

6.9

8.1

11.5

9.5

ns

tENHZ

Enable-Pad High to Z

8.3

9.7

11.1

13.0

18.5

15.2

ns

tENLZ

Enable-Pad Low to Z

8.3

9.7

11.1

13.0

18.5

15.2

ns

tGLH

G-to-Pad High

8.3

9.7

11.1

13.0

18.5

15.2

ns

tGHL

G-to-Pad Low

8.9

10.5

11.9

14.0

20.0

16.5

ns

tLSU

I/O Latch Output Set-Up

0.26

0.3

0.4

0.6

0.5

ns

tLH

I/O Latch Output Hold

0.0

ns

tLCO

I/O Latch Clock-Out (Pad-to-Pad) 32 I/O

8.4

9.8

11.1

13.1

18.7

15.4

ns

tACO

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

11.8

13.9

15.7

18.5

26.5

21.7

ns

dTLH

Capacitive Loading, Low to High

0.03

0.035

0.04

0.05

0.07

0.06

ns/pF

dTHL

Capacitive Loading, High to Low

0.04

0.05

0.06

0.07

0.10

0.08

ns/pF

tWDO

Hard-Wired Wide-Decode Output

0.04

0.045

0.05

0.06

0.09

0.07

ns

CMOS Output Module Timing1

tDLH

Data-to-Pad High

4.5

5.3

6.0

5.8

8.3

6.8

ns

tDHL

Data-to-Pad Low

3.7

4.3

4.9

7.1

10.1

8.3

ns

tENZH

Enable-Pad Z to High

4.8

5.6

6.4

7.5

10.7

8.8

ns

tENZL

Enable-Pad Z to Low

5.2

6.0

6.9

8.1

11.5

9.5

ns

tENHZ

Enable-Pad High to Z

8.3

9.7

11.1

13.0

18.5

15.2

ns

tENLZ

Enable-Pad Low to Z

8.3

9.7

11.1

13.0

18.5

15.2

ns

tGLH

G-to-Pad High

8.3

9.7

11.1

13.0

18.5

15.2

ns

tGHL

G-to-Pad Low

8.9

10.5

11.9

14.0

20.0

16.5

ns

tLSU

I/O Latch Set-Up

0.26

0.3

0.4

0.6

0.5

ns

tLH

I/O Latch Hold

0.0

ns

tLCO

I/O Latch Clock-Out (Pad-to-Pad)

32 I/O

9.9

11.6

13.2

15.5

22.3

18.2

ns

tACO

Array Latch Clock-Out (Pad-to-Pad) 32 I/O

13.9

16.3

18.5

21.8

31.2

25.6

ns

dTLH

Capacitive Loading, Low to High

0.04

0.05

0.06

0.07

0.10

0.08

ns/pF

dTHL

Capacitive Loading, High to Low

0.04

0.045

0.05

0.06

0.09

0.07

ns/pF

tWDO

Hard-Wired Wide-Decode Output

0.04

0.045

0.05

0.06

0.09

0.07

ns

Note:

1.

Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

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