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A1225DX-PQC 数据表(PDF) 44 Page - Actel Corporation |
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A1225DX-PQC 数据表(HTML) 44 Page - Actel Corporation |
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44 / 84 page  Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s 44 Discontinued – v3.0 A321 40DX Timing Char act eristics (Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C) ‘–2 Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed 3.3V ‘Std’ Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Logic Module Propagation Delays1 Combinatorial Functions tPD Internal Array Module Delay 1.8 2.3 2.8 3.6 3.2 ns tPDD Internal Decode Module Delay 1.9 2.5 3.0 3.8 3.5 ns Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.0 1.3 1.6 2.0 1.8 ns tRD2 FO=2 Routing Delay 1.4 1.9 2.2 2.8 2.5 ns tRD3 FO=3 Routing Delay 1.8 2.4 2.8 3.7 3.3 ns tRD4 FO=4 Routing Delay 2.2 2.9 3.4 4.5 4.0 ns tRD5 FO=8 Routing Delay 3.8 5.0 5.9 7.7 7.0 ns tRDD Decode-to-Output Routing Delay 0.5 0.7 0.78 1.0 0.91 ns Sequential Timing Characteristics3, 4 tCO Flip-Flop Clock-to-Output 2.1 2.8 3.3 4.3 3.9 ns tGO Latch Gate-to-Output 1.8 2.3 2.8 3.6 3.2 ns tSU Flip-Flop (Latch) Set-Up Time 0.3 0.4 0.47 0.6 0.55 ns tH Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 0.0 ns tRO Flip-Flop (Latch) Reset to Output 2.1 2.8 3.3 4.3 3.9 ns tSUENA Flip-Flop (Latch) Enable Set-Up 0.6 0.9 1.0 1.3 1.17 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 2.6 3.5 4.1 5.4 4.82 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 4.1 5.5 6.5 8.4 7.6 ns Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-Up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time. |
类似零件编号 - A1225DX-PQC |
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类似说明 - A1225DX-PQC |
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