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A1225DX-PLC 数据表(PDF) 49 Page - Actel Corporation |
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A1225DX-PLC 数据表(HTML) 49 Page - Actel Corporation |
49 / 84 page Discontinued – v3.0 49 Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies A322 00DX Timing Char act eristics (continued) (Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed 3.3V ‘Std’ Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Input Module Propagation Delays tINPY Input Data Pad-to-Y 1.4 1.65 1.9 2.2 2.9 2.5 ns tINGO Input Latch Gate-to-Output1 3.3 3.2 4.3 5.1 7.3 6.0 ns tINH Input Latch Hold1 0.0 0.0 0.0 0.0 0.0 0.0 ns tINSU Input Latch Set-Up1 0.45 0.52 0.6 0.7 1.0 0.8 ns tILA Latch Active Pulse Width1 4.4 5.2 5.9 6.9 9.8 8.1 ns Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 1.9 2.2 2.6 3.0 4.2 3.5 ns tIRD2 FO=2 Routing Delay 2.5 2.9 3.3 3.9 5.5 4.5 ns tIRD3 FO=3 Routing Delay 3.3 3.9 4.4 5.2 7.6 6.1 ns tIRD4 FO=4 Routing Delay 3.9 4.5 5.2 6.1 8.7 7.1 ns tIRD5 FO=8 Routing Delay 5.0 6.0 6.7 7.9 11.2 9.3 ns tIRDD Decode-to-Output Delay 0.3 0.37 0.4 0.5 0.7 0.6 ns Global Clock Network tCKH Input Low to High FO=32 FO=635 5.3 6.1 6.2 7.2 7.1 8.2 8.3 9.6 11.8 13.7 9.7 11.3 ns ns tCKL Input High to Low FO=32 FO=635 5.2 6.8 6.2 8.0 7.0 9.0 8.2 10.6 11.7 15.1 9.6 12.8 ns ns tPWH Minimum Pulse Width High FO=32 FO=635 2.7 2.9 3.2 3.45 3.7 3.9 4.3 4.6 6.1 6.6 5.0 5.4 ns ns tPWL Minimum Pulse Width Low FO=32 FO=635 2.7 2.9 3.2 3.45 3.7 3.9 4.3 4.6 6.1 6.6 5.0 5.4 ns ns tCKSW Maximum Skew FO=32 FO=635 0.6 0.6 0.75 0.75 0.9 0.9 1.0 1.0 1.4 1.4 1.1 1.1 ns ns tSUEXT Input Latch External Set-Up FO=32 FO=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=635 2.2 2.7 2.6 3.2 2.9 3.7 3.4 4.3 4.9 6.1 4.0 5.0 ns ns tP Minimum Period (1/fmax) FO=32 FO=635 5.5 6.1 6.5 7.2 7.4 8.2 8.7 9.6 12.4 13.7 10.2 11.2 ns ns fHMAX Maximum Datapath Frequency FO=32 FO=635 165 151 153. 140 132 121 115 105 80 73 98 90 MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. |
类似零件编号 - A1225DX-PLC |
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类似说明 - A1225DX-PLC |
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