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LT3837 数据表(PDF) 11 Page - Linear Technology |
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LT3837 数据表(HTML) 11 Page - Linear Technology |
11 / 28 page LT3837 11 3837fa OPERATION Minimum Output Switch On-Time (tON(MIN)) The LT3837 affects output voltage regulation via flyback pulse action. If the output switch is not turned on, there is no flyback pulse and output voltage information is not available. This causes irregular loop response and start-up/latch-up problems. The solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. If the output load is less than that developed under these conditions, forced continuous operation normally occurs. See Applications Information for further details. Enable Delay (ENDLY) The flyback pulse appears when the primary side switch shuts off. However, it takes a finite time until the trans- former primary side voltage waveform represents the output voltage. This is partly due to rise time on the pri- mary side MOSFET drain node but, more importantly, is due to transformer leakage inductance. The latter causes a voltage spike on the primary side, not directly related to output voltage. Some time is also required for internal settling of the feedback amplifier circuitry. In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay.” In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See Applications Information for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, which compares the flyback voltage (FB referred) to a fixed reference, nominally 80% of VFB. When the flyback waveform drops below this level, the feedback amplifier is disabled. Minimum Enable Time The feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed “minimum enable time.” This prevents lockup, especially when the output voltage is abnormally low; e.g., during start-up. The mini- mum enable time period ensures that the VC node is able to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. This time is internally set. Effects of Variable Enable Period The feedback amplifier is enabled during only a portion of the cycle time. This can vary from the fixed minimum enable time described to a maximum of roughly the “off” switch time minus the enable delay time. Certain parameters of flyback amp behavior are directly affected by the variable enable period. These include effective transconductance and VC node slew rate. Load Compensation Theory The LT3837 uses the flyback pulse to obtain information about the isolated output voltage. An error source is caused by transformer secondary current flow through the synchronous MOSFET RDS(ON)andreallifenonzeroimped- ances of the transformer secondary and output capacitor. This was represented previously by the expression “ISEC • (ESR + RDS(ON)).” However, it is generally more useful to convert this expression to effective output impedance. Because the secondary current only flows during the off portion of the duty cycle (DC), the effective output imped- ance equals the lumped secondary impedance divided by OFF time DC. Since the OFF time duty cycle is equal to 1 – DC then: R ESR R DC S OUT DS ON () () – = + 1 where: RS(OUT) = effective supply output impedance DC = duty cycle RDS(ON) and ESR are as defined previously This impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. In these cases the external FB resistive divider is adjusted to compensate for nominal expected error. In more demanding applications, output impedance error is minimized by the use of the load compensation function. |
类似零件编号 - LT3837 |
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类似说明 - LT3837 |
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