4-11

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

TC660

100mA CHARGE PUMP DC-TO-DC

VOLTAGE CONVERTER

clock frequency using TTL logic, the addition of a 10k

Ω pull-

up resistor to V

frequency with external clocking, as with internal clocking,

will be 1/2 of the clock frequency. Output transitions occur on

the positive-going edge of the clock.

It is also possible to increase the conversion efficiency

of the TC660 at low load levels by lowering the oscillator

frequency. This reduces the switching losses, and is achieved

Figure 7. Lowering the oscillator frequency will cause an

has been reduced. For example, the addition of a 100pF

capacitor between pin 7 (OSC) and GND will lower the

oscillator frequency to 1kHz from its nominal frequency of

10kHz (a multiple of 10), and necessitate a corresponding

Positive Voltage Doubler

Figure 5. Increased Output Voltage by Cascading Devices

1

2

3

4

8

7

6

5

V

+

1

2

3

4

8

7

6

5

150

µF

150

µF

150

µF

"n"

"1"

150

µF

VOUT

. VOUT = –n(V+) for 1.5V ≤ V+ ≤ 5.5V

NOTE:

*

*

+

+

+

+

TC660

TC660

Figure 6. External Clocking

1

2

3

4

8

7

6

5

TC660

+

V +

+

CMOS

GATE

150

µF

VOUT

150

µF

OSC

V +

Cascading Devices

The TC660 may be cascaded as shown (Figure 5) to

produce larger negative multiplication of the initial supply

voltage. However, due to the finite efficiency of each device,

the practical limit is 10 devices for light loads. The output

voltage is defined by:

where n is an integer representing the number of devices

cascaded. The resulting output resistance would be ap-

values.

Changing the TC660 Oscillator Frequency

It may be desirable in some applications (due to noise or

other considerations) to increase the oscillator frequency.

Pin 1, the FC pin, may be connected to V

oscillator frequency to 90kHz from a nominal of 10 kHz for

an input supply voltage of 5.0 volts. The oscillator may also

be synchronized to an external clock as shown in Figure 6

and LV must be grounded when overdriving OSC. In a

situation where the designer has generated the external

Figure 7. Lowering Oscillator Frequency

1

2

3

4

8

7

6

5

+

V

+

VOUT

C1

COSC

+

C2

TC660