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TELCOM SEMICONDUCTOR, INC.

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PRECISION ANALOG FRONT ENDS

FEATURES

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Precision (up to 17 Bits) A/D Converter "Front End"

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3-Pin Control Interface to Microprocessor

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Flexible: User Can Trade-Off Conversion Speed

for Resolution

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Single Supply Operation (TC510/514)

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4 Input, Differential Analog MUX (TC514)

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Automatic Input Voltage Polarity Detection

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Low Power Dissipation ........... TC500/500A: 10mW

TC510/514: 18mW

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Wide Analog Input Range .......

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Directly Accepts Bipolar and Differential Input

Signals

GENERAL DESCRIPTION

The TC500/500A/510/514 family are precision analog

front ends that implement dual slope A/D converters having

a maximum resolution of 17 bits plus sign. As a minimum,

each device contains the integrator, zero crossing compara-

tor and processor interface logic. The TC500 is the base

(16 bit max) device and requires both positive and negative

power supplies. The TC500A is identical to the TC500,

except it has improved linearity allowing it to operate to a

maximum resolution of 17 bits. The TC510 adds an on-

board negative power supply converter for single supply

operation. The TC514 adds both a negative power supply

converter and a 4 input differential analog multiplexer.

Each device has the same processor control interface

consisting of 3 wires: control inputs A and B and zero-

crossing comparator output (CMPTR). The processor ma-

nipulates A, B to sequence the TC5xx through four phases

of conversion: Auto Zero, Integrate, Deintegrate and Inte-

grator Zero. During the Auto Zero phase, offset voltages in

the TC5xx are corrected by a closed-loop feedback mecha-

nism. The input voltage is applied to the integrator during the

Integrate phase. This causes an integrator output dv/dt

directly proportional to the magnitude of the input voltage.

The higher the input voltage, the greater the magnitude of

the voltage stored on the integrator during this phase. At the

start of the Deintegrate phase, an external voltage reference

is applied to the integrator, and at the same time, the external

host processor starts its on-board timer. The processor main-

FUNCTIONAL BLOCK DIAGRAM

LEVEL

SHIFT

CONTROL LOGIC

ANALOG

SWITCH

CONTROL

SIGNALS

ACOM

+

VREF

+

–

BUF

CAZ

BUFFER

INTEGRATOR

SWR

–

SWIZ

CMPTR 1

CMPTR 2

CMPTR

OUTPUT

DGND

CONTROL LOGIC

SW1

TC500

TC500A

TC510

TC514

CREF

CREF

SWR

CREF

CAZ

RINT

CINT

CINT

SWRI

+

SWRI

+

SWRI

–

SWRI

SWZ

SWI

SWZ

VS

OSC

–

+

+

–

–

+

PHASE

DECODING

LOGIC

POLARITY

DETECTION

DC-TO-DC

CONVERTER

(TC510 & TC514)

–

+

A

B

0

0

ZERO INTEGRATOR OUTPUT

0

1

AUTO-ZERO

1

0

SIGNAL INTEGRATE

1

1

DEINTEGRATE

VREF

VOUT

COUT

1.0

µF

1.0

µF

VSS

–

–

–

SWI

B

A

A0

A1

DIF.

MUX

(TC514)

CH1

+

CH2

+

CH3

+

CH4

+

CH1

–

CH2

–

CH3

–

CH4

–

CAP– CAP+

(TC500

TC500A)

CONVERTER STATE

TC500

TC500A

TC510

TC514

TC500/A/510/514-3

10/3/96

ORDERING INFORMATION

Part No.

Package

Temp. Range

TC500ACOE

16-Pin SOIC

0

°C to +70°C

TC500ACPE

16-Pin Plastic DIP (Narrow)

0

°C to +70°C

TC500COE

16-Pin SOIC

0

°C to +70°C

TC500CPE

16-Pin Plastic DIP (Narrow)

0

°C to +70°C

TC510COG

24-Pin SOIC

0

°C to +70°C

TC510CPF

24-Pin Plastic DIP (300 Mil.)

0

°C to +70°C

TC514COI

28-Pin SOIC

0

°C to +70°C

TC514CPJ

28-Pin Plastic DIP (300 Mil.)

0

°C to +70°C

TC500EV

Evaluation Kit for TC500/500A/510/514

EVALUATION

KIT

AVAILABLE