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LT1943 数据表(PDF) 10 Page - Linear Technology |
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LT1943 数据表(HTML) 10 Page - Linear Technology |
10 / 20 page LT1943 10 1943fa OPERATIO Figure 2. LT1943 Power-Up Sequence. (Traces From Both Photos are Synchronized to the Same Trigger) RUN-SS 2V/DIV VLOGIC 5V/DIV IL1 1A/DIV IL2+L3 1A/DIV SS-234 2V/DIV AVDD 20V/DIV PGOOD 20V/DIV 5ms/DIV 1943 F03a VOFF 10V/DIV VCT 2V/DIV IL4 500mA/DIV IL5 500mA/DIV VE3 20V/DIV VON 50V/DIV 5ms/DIV 1943 F03b (2a) (2b) The LT1943 is a highly integrated power supply IC con- taining four separate switching regulators. All four switch- ing regulators have their own oscillator with frequency foldback and use current mode control. Switching regula- tor 1 consists of a step-down regulator with a switch current limit of 2.4A. Switching regulator 2 can be config- ured as a step-up or SEPIC converter and has a 2.6A switch. Switching regulator 3 consists of a step-up regu- lator with a 0.35A switch as well as an integrated Schottky diode. Switching regulator 4 has two feedback pins (FB4 and NFB4) and can directly regulate positive or negative output voltages. The four regulators share common cir- cuitry including input source, voltage reference, and mas- ter oscillator. Operation can be best understood by refer- ring to the Block Diagram as shown in Figure 1. If the RUN/SS pin is pulled to ground, the LT1943 is shut down and draws 35 µAfromtheinputsourcetiedtoVIN.An internal 1.7 µA current source charges the external soft- start capacitor, generating a voltage ramp at this pin. If the RUN/SS pin exceeds 0.6V, the internal bias circuits turn on, including the internal regulator, reference, and 1.1MHz master oscillator. The master oscillator generates four clock signals, one for each of the switching regulators. Switching regulator 1 will only begin to operate when the RUN/SS pin reaches 0.8V. Switcher 1 generates VLOGIC, which must be tied to the BIAS pin. When BIAS reaches 2.8V, the NPN pulling down on the SS-234 pin turns off, allowing an internal 1.7 µA current source to charge the external capacitor tied to the SS-234 pin. When the voltage on the SS-234 pin reaches 0.8V, switchers 2, 3 and 4 are enabled. AVDD and VOFF will then begin rising at a ramp rate determined by the capacitor tied to the SS-234 pin. When all the outputs reach 90% of their programmed voltages, the NPN pulling down on the CT pin will turn off, and an internal 20 µA current source will charge the exter- nal capacitor tied to the CT pin. When the CT pin reaches 1.1V, the output disconnect PNP turns on, connecting VON. In the event of any of the four outputs dropping below 10% of their programmed voltage, PanelProtect circuitry pulls the CT pin to GND, disabling VON. A power good comparator monitors AVDD and turns on when the FB2 pin is at or above 90% of its regulated value. The output is an open collector transistor that is off when the output is out of regulation, allowing an external resis- tor to pull the pin high. This pin can be used with a P-channel MOSFET that functions as an output disconnect for AVDD. The four switchers are current mode regulators. Instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. Compared to voltage mode control, current mode control improves loop dynamics and pro- vides cycle-by-cycle current limit. |
类似零件编号 - LT1943 |
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类似说明 - LT1943 |
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