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EP2C35A5Q324I8N 数据表(PDF) 68 Page - Altera Corporation |
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EP2C35A5Q324I8N 数据表(HTML) 68 Page - Altera Corporation |
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68 / 168 page  2–56 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 I/O Structure & Features Cyclone II devices support driver impedance matching to the impedance of the transmission line, typically 25 or 50 Ω. When used with the output drivers, on-chip termination sets the output driver impedance to 25 or 50 Ω. Cyclone II devices also support I/O driver series termination (RS = 50 Ω) for SSTL-2 and SSTL-18. Table 2–19 lists the I/O standards that support impedance matching and series termination. 1 The recommended frequency range of operation is pending silicon characterization. On-chip series termination can be supported on any I/O bank. VCCIO and VREF must be compatible for all I/O pins in order to enable on-chip series termination in a given I/O bank. I/O standards that support different RS values can reside in the same I/O bank as long as their VCCIO and VREF are not conflicting. 1 When using on-chip series termination, programmable drive strength is not available. Impedance matching is implemented using the capabilities of the output driver and is subject to a certain degree of variation, depending on the process, voltage and temperature. The actual tolerance is pending silicon characterization. Table 2–19. I/O Standards Supporting Series Termination Note (1) I/O Standards Target RS ( Ω)VCCIO (V) 3.3-V LVTTL and LVCMOS 25 (2) 3.3 2.5-V LVTTL and LVCMOS 50 (2) 2.5 1.8-V LVTTL and LVCMOS 50 (2) 1.8 SSTL-2 class I 50 (2) 2.5 SSTL-18 class I 50 (2) 1.8 Notes to Table 2–19: (1) Supported conditions are VCCIO =VCCIO ±50 mV. (2) These RS values are nominal values. Actual impedance varies across process, voltage, and temperature conditions. |
类似零件编号 - EP2C35A5Q324I8N |
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类似说明 - EP2C35A5Q324I8N |
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