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EP2C35A5F324C7N 数据表(PDF) 71 Page - Altera Corporation

部件名 EP2C35A5F324C7N
功能描述  Cyclone II Device Family
Download  168 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP2C35A5F324C7N 数据表(HTML) 71 Page - Altera Corporation

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Altera Corporation
2–59
February 2007
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
Figure 2–29. EP2C15, EP2C20, EP2C35, EP2C50 & EP2C70 I/O Banks
Notes (1), (2)
Notes to Figure 2–29:
(1)
This is a top view of the silicon die.
(2)
This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
(3)
The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
(4)
The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
(5)
The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
Each I/O bank has its own VCCIO pins. A single device can support
1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support
a different standard with different I/O voltages. Each bank also has
dual-purpose VREF pins to support any one of the voltage-referenced
I/O Bank 2
Regular I/O Block
Bank 8
Regular I/O Block
Bank 7
I/O Bank 3
I/O Bank 4
I/O Bank 1
I/O Bank 5
I/O Bank 6
Individual
Power Bus
All I/O Banks Support
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
LVDS
RSDS
mini-LVDS
LVPECL (3)
SSTL-2 Class I and II
SSTL-18 Class I
HSTL-18 Class I
HSTL-15 Class I
Differential SSTL-2 (4)
Differential SSTL-18 (4)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
I/O Banks 3 & 4 Also Support
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
I/O Banks 7 & 8 Also Support
the SSTL-18 Class II,
HSTL-18 Class II, & HSTL-15
Class II I/O Standards
I/O Banks 5 & 6 Also
Support the 3.3-V PCI
& PCI-X I/O Standards
I/O Banks 1 & 2 Also
Support the 3.3-V PCI
& PCI-X I/O Standards


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