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EP2C35A5F324I6N 数据表(PDF) 32 Page - Altera Corporation |
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EP2C35A5F324I6N 数据表(HTML) 32 Page - Altera Corporation |
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32 / 168 page  2–20 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Global Clock Network & Phase-Locked Loops Dedicated Clock Pins Larger Cyclone II devices (EP2C15 and larger devices) have 16 dedicated clock pins (CLK[15..0], four pins on each side of the device). Smaller Cyclone II devices (EP2C5 and EP2C8 devices) have eight dedicated clock pins (CLK[7..0], four pins on left and right sides of the device). These CLK pins drive the global clock network (GCLK), as shown in Figures 2–11 and 2–12. If the dedicated clock pins are not used to feed the global clock networks, they can be used as general-purpose input pins to feed the logic array using the MultiTrack interconnect. However, if they are used as general- purpose input pins, they do not have support for an I/O register and must use LE-based registers in place of an I/O register. Dual-Purpose Clock Pins Cyclone II devices have either 20 dual-purpose clock pins, DPCLK[19..0] or 8 dual-purpose clock pins, DPCLK[7..0]. In the larger Cyclone II devices (EP2C15 devices and higher), there are 20 DPCLK pins; four on the left and right sides and six on the top and bottom of the device. The corner CDPCLK pins are first multiplexed before they drive into the clock control block. Since the signals pass through a multiplexer before feeding the clock control block, these signals incur more delay to the clock control block than other DPCLK pins that directly feed the clock control block. In the smaller Cyclone II devices (EP2C5 and EP2C8 devices), there are eight DPCLK pins; two on each side of the device (see Figures 2–11 and 2–12). A programmable delay chain is available from the DPCLK pin to its fan- out destinations. To set the propagation delay from the DPCLK pin to its fan-out destinations, use the Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations assignment in the Quartus II software. These dual-purpose pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as TRDY and IRDY for PCI, or DQS signals for external memory interfaces. |
类似零件编号 - EP2C35A5F324I6N |
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类似说明 - EP2C35A5F324I6N |
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