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EP2C35A5Q324C6N 数据表(PDF) 67 Page - Altera Corporation |
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EP2C35A5Q324C6N 数据表(HTML) 67 Page - Altera Corporation |
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67 / 168 page  Altera Corporation 2–55 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture You can use I/O pins and internal logic to implement a high-speed I/O receiver and transmitter in Cyclone II devices. Cyclone II devices do not contain dedicated serialization or deserialization circuitry. Therefore, shift registers, internal PLLs, and IOEs are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. The maximum internal clock frequency for a receiver and for a transmitter is 402.5 MHz. The maximum input data rate of 805 Mbps and the maximum output data rate of 640 Mbps is only achieved when DDIO registers are used. The LVDS standard does not require an input reference voltage, but it does require a 100- Ωtermination resistor between the two signals at the input buffer. An external resistor network is required on the transmitter side. f For more information on Cyclone II differential I/O interfaces, see the High-Speed Differential Interfaces in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook. Series On-Chip Termination On-chip termination helps to prevent reflections and maintain signal integrity. This also minimizes the need for external resistors in high pin count ball grid array (BGA) packages. Cyclone II devices provide I/O driver on-chip impedance matching and on-chip series termination for single-ended outputs and bidirectional pins. EP2C70 672 160 (168) 896 257 (265) Note to Table 2–18: (1) The first number represents the number of bidirectional I/O pins which can be used as inputs or outputs. The number in parenthesis includes dedicated clock input pin pairs which can only be used as inputs. Table 2–18. Cyclone II Device LVDS Channels (Part 2 of 2) Device Pin Count Number of LVDS Channels (1) |
类似零件编号 - EP2C35A5Q324C6N |
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类似说明 - EP2C35A5Q324C6N |
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