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AT86RF212-ZU 数据表(PDF) 7 Page - ATMEL Corporation

部件名 AT86RF212-ZU
功能描述  Low Power 800/900 MHz Transceiver for IEEE 802.15.4- 2006, ZigbeeTM, and ISM Applications
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

AT86RF212-ZU 数据表(HTML) 7 Page - ATMEL Corporation

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8168A-AVR-06/08
AT86RF212
2.2.1.3 Crystal Oscillator Pins
XTAL1, XTAL2
The pin XTAL1 is the input of the reference oscillator amplifier (XOSC), XTAL2 the
output. A detailed description of the crystal oscillator setup and the related
XTAL1/XTAL2 pin configuration can be found in section 7.7.
When using an external clock reference signal, XTAL1 shall be used as input pin. For
further details refer to section 7.7.3.
2.2.1.4 Analog Pin Summary
Table 2-2. Analog Pin Behavior – DC values
Pin
Values and Conditions
Comments
RFP/RFN
VDC = 0.9 V (BUSY_TX)
VDC = 20 mV (receive states)
VDC = 0 mV (otherwise)
DC level at pins RFP/RFN for various transceiver states
AC-coupling is required if an antenna with a DC path to ground is
used. Serial capacitance and capacitance of each pin to ground
must be < 100 pF.
XTAL1/XTAL2
VDC = 0.9 V at both pins
CPAR = 3 pF
VAC ≤ 1.0 Vpp
DC level at pins XTAL1/XTAL2 for various transceiver states
Parasitic capacitance (Cpar) of the pins must be considered as
additional load capacitance to the crystal.
DVDD
VDC = 1.8 V (all states, except P_ON, SLEEP,
and RESET)
VDC = 0 mV (otherwise)
DC level at pin DVDD for various transceiver states
Supply pins (voltage regulator output) for the digital 1.8 V voltage
domain. The outputs shall be bypassed by 1 µF.
AVDD
VDC = 1.8 V (all states, except P_ON, SLEEP,
RESET, and TRX_OFF)
VDC = 0 mV (otherwise)
DC level at pin AVDD for various transceiver states
Supply pin (voltage regulator output) for the analog 1.8 V voltage
domain. The outputs shall be bypassed by 1 µF.
2.2.2 Digital Pins
The AT86RF212 provides a digital microcontroller interface. The interface comprises a
slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ,
SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in chapter
4.
Additional digital output signals DIG1 … DIG4 are provided to control external blocks,
i.e. for Antenna Diversity RF switch control or as an RX/TX Indicator, see sections 9.3
and 9.4, respectively. After reset, these pins are connected to digital ground
(DIG1/DIG2) or analog ground (DIG3/DIG4).
2.2.2.1 Driver Strength Settings
The driver strength of all digital output pins (MISO, IRQ, DIG1, …, DIG4) and CLKM pin
can be configured using register 0x03 (TRX_CTRL_0), see Table 2-3.
Table 2-3. Digital Output Driver Configuration
Pin
Default Driver Strength
Comment
MISO, IRQ, DIG1, …, DIG4
2 mA
Adjustable to 2 mA, 4 mA, 6 mA, and 8 mA
CLKM
4 mA
Adjustable to 2 mA, 4 mA, 6 mA, and 8 mA
The capacitive load should be as small as possible and not larger than 50 pF when
using the 2 mA minimum driver strength setting. Generally, the output driver strength


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