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DP83848H 数据表(PDF) 55 Page - National Semiconductor (TI) |
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DP83848H 数据表(HTML) 55 Page - National Semiconductor (TI) |
55 / 80 page 55 www.national.com 5 LED_CNFG[0] Strap, RW LED Configuration LED_ CNFG[0] Mode Description 1 Mode 1 0 Mode2 In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity 4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port. Table 27. PHY Control Register (PHYCR), address 0x19 (Continued) Bit Bit Name Default Description |
类似零件编号 - DP83848H |
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类似说明 - DP83848H |
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