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EPLD Datasheet(数据表) 1 Page - Altera Corporation

部件型号  EPLD
说明  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
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EPLD Datasheet(HTML) 1 Page - Altera Corporation

 
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®
Altera Corporation
745
Classic
EPLD Family
May 1999, ver. 5
Data Sheet
A-DS-CLASSIC-05
Features
s
Complete device family with logic densities of 300 to 900 usable gates
(see Table 1)
s
Device erasure and reprogramming with non-volatile EPROM
configuration elements
s
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
s
24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
s
Programmable security bit for protection of proprietary designs
s
100% generically tested to provide 100% programming yield
s
Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
s
Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
s
Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
s
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
EP610
EP610I
EP910
EP910I
EP1810
Usable gates
300
450
900
Macrocells
16
24
48
Maximum user I/O pins
22
38
64
tPD (ns)
10
12
20
fCNT (MHz)
100
76.9
50




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