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EPLD Datasheet(数据表) 5 Page - Altera Corporation

部件型号  EPLD
说明  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
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EPLD Datasheet(HTML) 5 Page - Altera Corporation

 
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Altera Corporation
749
Classic EPLD Family Data Sheet
Figure 2. Classic Output Enable/Clock Select
Feedback Select
Each macrocell in a Classic device provides feedback selection that is
controlled by the feedback multiplexer. This feedback selection allows the
designer to feed either the macrocell output or the I/O pin input
associated with the macrocell back into the AND array. The macrocell
output can be either the Q output of the programmable register or the
combinatorial output of the macrocell. Different devices have different
feedback multiplexer configurations. See Figure 3.
Figure 3. Classic Feedback Multiplexer Configurations
In Mode 0, the register
is clocked by the global
clock signal. The
output is enabled by
the logic from the
product term.
Macrocell
Output Buffer
Global
Clock
OE
CLK
AND
Array
Data
Output Enable/Clock
Select
OE = Product Term
CLK = Global
Mode 0
In Mode 1, the output
is permanently enabled
and the register is
clocked by the product
term, which allows
gated clocks to be
generated.
OE = Enabled
CLK = Product Term
Mode 1
Output Enable/Clock
Select
VCC
CLR
Q
Macrocell
Output Buffer
Global
Clock
VCC
OE
CLK
AND
Array
Data
CLR
Q
Q
I/O
EP610
EP610I
EP910
EP910I
EP1810
Q
I/O
EP1810
Q
I/O
Global
Quadrant
Quadrant
Global
Global Feedback Multiplexer
Quadrant Feedback Multiplexer
Dual Feedback Multiplexer




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