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ACEX1K 数据表(PDF) 30 Page - Altera Corporation |
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ACEX1K 数据表(HTML) 30 Page - Altera Corporation |
30 / 86 page 30 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Figure 15. ACEX 1K Bidirectional I/O Registers VCC OE[7..0] CLK[1..0] ENA[5..0] CLRN[1..0] Peripheral Control Bus CLRN DQ ENA VCC 2 Dedicated Clock Inputs Slew-Rate Control Open-Drain Output Chip-Wide Output Enable CLK[3..2] 2 12 VCC VCC Chip-Wide Reset Programmable Delay 4 Dedicated Inputs Row and Column Interconnect 4 VCC CLRN DQ ENA Chip-Wide Reset CLRN DQ ENA Chip-Wide Reset VCC Input Register Output Register OE Register |
类似零件编号 - ACEX1K_03 |
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类似说明 - ACEX1K_03 |
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