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ACEX1K_03 Datasheet(数据表) 2 Page - Altera Corporation

部件型号  ACEX1K
说明  Programmable Logic Device Family
下载  86 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
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ACEX1K Datasheet(HTML) 2 Page - Altera Corporation

 
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2
for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
Operate with a 2.5-V internal supply voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
Built-in, low-skew clock distribution trees
–100% functional testing of all devices; test vectors or scan chains
are not required
Pull-up on I/O pins before and during configuration
Flexible interconnect
–FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Powerful I/O pins
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
–Clamp to VCCIO user-selectable on a pin-by-pin basis
Supports hot-socketing




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