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T89C5115 数据表(PDF) 90 Page - ATMEL Corporation |
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T89C5115 数据表(HTML) 90 Page - ATMEL Corporation |
90 / 113 page 90 AT89C5115 4128G–8051–02/08 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination. Table 66. Priority Level bit Values A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, See Table 67. Table 67. Interrupt Priority Within Level IPH.x IPL.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) Interrupt Name Interrupt Address Vector Priority Number External interrupt (INT0) 0003h 1 Timer0 (TF0) 000Bh 2 External interrupt (INT1) 0013h 3 Timer 1 (TF1) 001Bh 4 PCA (CF or CCFn) 0033h 5 UART (RI or TI) 0023h 6 Timer 2 (TF2) 002Bh 7 ADC (ADCI) 0043h 9 |
类似零件编号 - T89C5115 |
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类似说明 - T89C5115 |
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