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MPC5123YVY300BR 数据表(PDF) 78 Page - Freescale Semiconductor, Inc |
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MPC5123YVY300BR 数据表(HTML) 78 Page - Freescale Semiconductor, Inc |
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78 / 86 page  MPC5121E/MPC5123 Data Sheet, Rev. 1 System Design Information Freescale Semiconductor 78 4.5.1.1 TRST and PORESET The JTAG interface can control the direction of the MPC5121e/MPC5123 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5121e/MPC5123 comes out of power-on reset; do this by asserting TRST before PORESET is released. For more details refer to the Reset and JTAG Timing Specification. Figure 60. PORESET vs. TRST 4.5.2 e300 COP/BDM Interface There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector. 4.5.2.1 Boards Interfacing the JTAG Port via a COP Connector The MPC5121e/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale standard COP/BDM interface. Table 52 gives the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order. Table 52. COP/BDM Interface Signals BDM Pin # MPC5121e/MPC51 23 I/O Pin BDM Connector Internal Pull Up/Down External Pull Up/Down I/O1 16 — GND — — — 15 CKSTP_OUT ckstp_out — 10k Pull-Up I 14 — KEY — — — 13 HRESET hreset Pull-Up 10k Pull-Up O 12 — GND — — — 11 SRESET sreset Pull-Up 10k Pull-Up O 10 — N/C — — — 9 TMS tms Pull-Up 10k Pull-Up O 8 CKSTP_IN ckstp_in — 10k Pull-Up O 7 TCK tck Pull-Up 10k Pull-Up O 6— VDD2 —— — 5See Note3 halted3 —— I 4TRST trst Pull-Up 10k Pull-Up O 3 TDI tdi Pull-Up 10k Pull-Up O TRST PORESET Required assertion of TRST Optional assertion of TRST Preliminary |
类似零件编号 - MPC5123YVY300BR |
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类似说明 - MPC5123YVY300BR |
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