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MPC5123YVY300BR 数据表(PDF) 71 Page - Freescale Semiconductor, Inc |
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MPC5123YVY300BR 数据表(HTML) 71 Page - Freescale Semiconductor, Inc |
71 / 86 page Electrical and Thermal Characteristics MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor 71 Figure 50. Timing Diagram – SPI Master Mode, Format 1 (CPHA = 1) NOTE Output timing is specified at a nominal 50 pF load. Table 47. Timing Specifications – SPI Slave Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A20.56 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A20.57 3 Slave select clock delay 0.0 — ns A20.58 4 Output data valid — 14.0 ns A20.59 5 Input Data setup time 2.0 — ns A20.60 6 Input Data hold time 1.0 — ns A20.61 7 Slave disable lag time 0.0 — ns A20.62 8 Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time 30.0 — ns A20.63 SCK (CLKPOL=0) SCK (CLKPOL=1) MOSI Output Output Output SS Output MISO Input 1 22 7 8 3 4 6 10 9 9 10 5 Preliminary |
类似零件编号 - MPC5123YVY300BR |
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类似说明 - MPC5123YVY300BR |
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